1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device and, particularly to a semiconductor device and manufacturing method thereof in which a bipolar transistor is formed on a substrate or both a bipolar transistor and a complementary MOS (CMOS) transistor are formed on the same substrate.
2. Description of the Related Art
According to a conventional semiconductor device manufacturing method as described above, as shown in FIG. 1, an n-type epitaxial layer 36 is formed on a p-type silicon substrate 1 on which an n-type buried layer 34 and a p-type buried layer 35 are formed, and then a field oxide film 2 is formed at a thickness of 3000 to 6000 angstroms by LOCOS method. Thereafter, an n-well region 7, a base region 6 of a bipolar transistor and an n-type collector leading region 4 are formed, and then a gate oxide film 3 of 50 to 200 angstroms in film thickness is formed.
Subsequently, as shown in FIG. 2, a polysilicon layer of 1500 to 2000 angstroms which is formed on the whole surface is patterned to form a PMOS gate electrode 12 and an NMOS gate electrode 13. Thereafter, an oxide film is deposited at a thickness of 1000 angstroms, and an anisotropic dry etching is performed to form side walls 14, 14' on the side surfaces of the gate electrodes 12, 13 respectively. Subsequently, boron is doped at a dose amount of 5 to 9.times.10.sup.10 cm.sup.-2 into a graft base region 15 of the bipolar transistor, the gate electrode 12 of PMOS transistor and the source and drain regions 16 of PMOS transistor by ion implantation. Arsenic is doped at a dose amount of 1 to 2.times.10.sup.16 cm.sup.-2 into the gate electrode 13 of NMOS transistor and the source and drain regions 17 of NMOS transistor by ion implantation. Phosphor may be used as n-type impurities.
Subsequently, as shown in FIG. 3, an emitter contact (opening) 19 is formed in an oxide film 18 of 1000 to 2000 angstroms in thickness which are grown on the whole surface, and then a polysilicon layer is formed at a thickness of 1500 to 2000 angstroms on the overall surface. Subsequently, arsenic is doped at a dose amount of 1 to 2.times.10.sup.16 cm.sup.-2 into the polysilicon layer by ion implantation, and then the polysilicon layer is patterned to form an emitter electrode 20 of the bipolar transistor. Thereafter, a heat treatment is performed to diffuse arsenic from the polysilicon layer of the emitter electrode 20 to the base region 6, thereby forming an emitter region 22.
Next, as shown in FIG. 4, an interlayer insulating film 23 is deposited on the elements which have been formed through the above process, and a contact (opening) 24 is formed therein. Thereafter, a plug 25 of tungsten or the like is formed in the contact 24, and each metal wire 26 is formed to thereby complete a semiconductor device.
In the case of the above-described method, if the concentration of the impurities of the n-type epitaxial layer 36 is set to a low value (about 1 to 5.times.10.sup.15 cm.sup.-2) and the n-type buried layer 34 which is connected to the collector leading region 4 and contains impurities at high concentration is provided below the n-type epitaxial layer 36, not only the collector resistance of the bipolar transistor can be reduced, but also the withstanding voltage of the bipolar transistor can be prevented from being reduced. However, this method needs a lithography process and a heat treatment process for formation of the buried layers, and an epitaxial growth process, and thus it has a disadvantage that the manufacturing cost necessarily rises up. As a method of solving this problem, K. Ishimaru, et al. ("International Electron Device Meeting", 1995, pp. 673) has proposed a manufacturing method which needs no buried layer forming process and no epitaxial growth process.
The proposed manufacturing method will be described with reference to FIGS. 5 to 8.
First, as shown in FIG. 5, a field oxide film 2 of 3000 to 6000 angstroms in thickness is formed on a p-type silicon substrate 1 by the LOCOS method, and then a gate oxide film 3 is grown to have a thickness of 50 to 200 angstroms. Subsequently, ion-implantation processes are performed by using as a mask in each process a patterned photoresist layer (not shown) formed by a photolithography process to thereby form an n-type collector leading region 4, a buried collector region 5 and a base region 6 of a bipolar transistor and an n-well region 7 for PMOS transistor and a p-well region 9 for NMOS transistor. The collector resistance of the bipolar transistor can be reduced by increasing the dose amount of the n-type impurities which are doped to form the buried collector region 5.
Subsequently, as shown in FIG. 6, a polysilicon layer which is grown at a thickness of 1500 to 2000 angstroms on the overall surface is etched to form a gate electrode 12 of PMOS transistor and a gate electrode 13 of NMOS transistor. Thereafter, an oxide film is deposited at a thickness of 1000 angstroms, and then an anisotropic dry etching treatment is performed to form side walls 14, 14' on the side surfaces of the gate electrodes 12 and 13, respectively. Subsequently, boron is doped at a dose amount of 5 to 9.times.10.sup.16 cm.sup.-2 into a graft base region 15 of the bipolar transistor and the gate electrode 12 and the source and drain regions 16 of PMOS transistor by ion implantation. Further, arsenic is doped at a dose amount of 1 to 2.times.10.sup.16 cm.sup.-2 into the gate electrode 13 and the source and drain regions 17 of NMOS transistor by ion implantation. Phosphor may be used as the n-type impurities.
Subsequently, as shown in FIG. 7, an emitter contact 19 is formed in an oxide film 18 which is grown at a thickness of 1000 to 2000 angstroms on the overall surface, and then a polysilicon layer is grown at a thickness of 1500 to 2000 angstroms on the overall surface. Thereafter, arsenic is doped at a dose amount of 1 to 2.times.10.sup.16 cm.sup.-2 into the polysilicon layer by ion implantation, and the polysilicon layer is patterned to form an emitter electrode 20 of the bipolar transistor. Thereafter, the heat treatment is performed in a nitrogen atmosphere at 850 to 900.degree. C. to activate the ion-implanted impurities. At this time, arsenic is diffused from the polysilicon layer of the emitter electrode 20 of the bipolar transistor to the base region 6 to form an emitter region 22.
Subsequently, as shown in FIG. 8, an interlayer insulating film 23 is deposited on the elements formed in the above process, and a contact 24 is formed. Thereafter, a plug 25 of tungsten or the like is formed, and each metal wire 26 is formed to thereby complete a semiconductor device.
According to the above manufacturing method, the concentration of the doped impurities to form the buried collector region 5 is increased to reduce the collector resistance. However, as shown in FIG. 9, the increase of the amount of the doped impurities causes increase in the concentration of donors in an area which come into contact with the high-concentration p-type impurities diffusing region (the graft base area 15 of the bipolar transistor), so that parasitic capacitance is increased and the withstanding voltage is reduced.
As described above, in the conventional manufacturing method, if the collector resistance of the bipolar transistor is increased, the number of manufacturing steps is increased, and also the increase of the parasitic capacitance of the transistor and the reduction of the withstanding voltage are caused.